Sixty years after Singapore achieved independence, Andrew Tay is clearly a successful example of his government’s early drive to establish a thriving republic after the end of British rule. Enrolled in one of the two technical schools founded to educate Singapore’s youth in science and technology, Tay became interested in engineering and went on to the University of New South Wales, Australia, to study Mechanical Engineering on a Colombo Plan scholarship. He stayed on to earn his Ph.D. there, applying the finite element method to calculate temperature distributions generated during metal cutting.
Upon his return to Singapore, he worked briefly in the Ministry of Science and Technology. But he found his true calling when he came back to academia at the National University of Singapore to teach several generations of engineers about the intricacies of simulating the manufacturing and packaging of microelectronics (i.e. the integrated circuits found in everything from cell phones to satellites). His four decades of research is still cited by others and applied throughout the chip-design industry.
SIMULIA Community News (SCN): When did you first begin applying finite element analysis (FEA) to solve problems in microelectronics chips design?
TAY: FEA is a fantastic tool for engineers to solve practical engineering problems. My Ph.D. supervisor Graeme De Vahl Davis and I published the first reported application of the finite-element method to convective heat transfer back in 1971. But even before the commercial availability of FEA, I had been writing my own programs—back in the days when we were using the IBM computer punch-card system! I had to generate finite element meshes manually using graph paper and transparencies.
We started out using Nastran in the 1980s, but then subscribed to Abaqus because it was the only software company that gave us a good price for a full-sized program. We were trying to solve real-world problems so we needed more capabilities than an educational version could provide. The developers at SIMULIA brought in package capabilities pretty quickly and, later, the new fracture mechanics methodology has been very useful to my research in IC chips and packages.
SCN: What do you like most about teaching?
TAY: When you teach a course, you really have to know everything about the subject. As I teach the finite element method, I have a deep understanding of the method as I have developed my own programs and solution techniques. Teaching is very satisfying for me because students are learning something from you. After your lecture, when you can answer their queries and see that they understood your explanations, you feel happy that you’ve been able to impart some knowledge to them.
SCN: What are currently working on?
TAY: I have just left my Professorship at the National University of Singapore after 40 years and am now doing research with the Singapore University of Technology and Design, which was set up recently in collaboration with MIT. We are working on the reliability of solar cell modules, which are actually a lot like big electronics packages. The scale of computer chips for things like mobile phones is very small and in solar cells it’s obviously much larger. But each solar cell is essentially like a chip, although with far fewer interconnects. So I’m doing similar work to what I’ve done in the past, computing the stresses in the solar modules when they are fabricated and operated. No matter what the size of the chip package, the stresses arise because different materials stuck together have different rates of expansion.
SCN: You sound like you are definitely staying in touch with current developments. What directions do you see electronics packaging taking next?
TAY: At the microcircuit level, the internal-feature size for the chips continues to get ever smaller. When you are designing chips, you have to be doing both global and local analysis. The feature sizes of microelectronic chips and products can range from tens of nanometers to centimeters and even meters. Thus multiscale or sub-modeling is becoming a necessity. Abaqus has this kind of sub-modeling capability, and it needs to become as straightforward and robust as possible to help designers solve the challenges of such tiny packages, where we will still be dealing with issues such as cracking and delamination.
With the development of wearable electronics, chips also have to be very thin with flexible wires, and sometimes even washable if they are incorporated into clothing. These are big challenges of large displacements, for which we do already have the simulation tools.
In the near future, microelectronics packaging will be driven by the Internet of Things (IoT) which is defined by Wikipedia as the network of physical objects or “things” embedded with electronics, software, sensors, and network connectivity, which enables these objects to collect and exchange data. As sensors and chips have to be very small, especially for mobile applications, 3D packaging of chips has to be further developed. The 3D integration of sensors, microprocessors and memory chips for IoT also has to be developed. As time-to-market is always an important consideration for the success of consumer products, simulation is becoming a crucial process whereby virtual prototyping and optimization can be done quickly and economically.
